1. Field of the Invention
The present invention generally relates to the field of integrated circuits and more particularly to vertical insulated gate transistors.
The invention applies in particular, although not exclusively, to high-speed logic circuits and radio-frequency circuits. More generally, the invention finds an application in technologies below 0.07 micron.
2. Description of Related Art
The vertical transistor is a device that overcomes the limitations of the planar MOS transistor, in lengths less than 0.1 micron. Its conduction body consists of a silicon pillar insulated and covered by a gate. It therefore has at least two conduction interfaces. Accordingly, the current Ion and the transconductance per unit width are at least doubled. For sufficiently fine silicon pillars, with a dimension of the order of 50 nm, coupling between the gates is observed, reducing the effects of the short channels. This makes it possible to reduce the doping of the pillar, which is particularly favorable from the point of view of the current Ion. Also, conduction over a plurality of interfaces, in conjunction with the coupling of the gates, makes it possible to eliminate the need to form ultrafine gate oxides or high-permittivity dielectrics.
What is more, the vertical transistor is a technological platform particularly suitable for implementing a coating gate architecture with ultrashort dimensions. This is because the channel length in the vertical transistor is not fixed by the photolithographic resolution. It is therefore possible to form channels with very small dimensions using standard photolithographic equipment. Also, coating a projecting silicon pillar with a gate is much simpler than coating a thin silicon film buried in a substrate.
The person skilled in the art knows of many methods of fabricating a vertical insulated gate transistor, using different techniques to form the silicon pillar. In a first approach, the silicon pillar is etched anisotropically from a silicon layer grown epitaxially from the isolated substrate.
In a second, more sophisticated approach, the pillar is grown epitaxially, overflowing into an open window in a dielectric layer.
The first approach draws its inspiration largely from steps of the conventional method of producing a planar transistor. In particular, forming the pillar by etching resembles etching the gate of a planar transistor. The pillar is doped after it is formed, although it could be doped during epitaxial growth or before etching. The source and drain regions are implanted in a self-aligned manner relative to the pillar. The source can also be implanted before epitaxial growth, in which case it is referred to as “continuous” (the source areas on either side of the pillar are joined together). The gate oxide is then formed on the flanks of the silicon pillar. The polysilicon gate is then deposited, doped and then etched.
This kind of approach, which is simple to implement, makes it possible to develop a CMOS line based on vertical transistors at reduced cost.
With the second approach, the epitaxially grown pillar is planarized by mechanical/chemical polishing. The benefit of the second approach is that it leaves at the base of the pillar a thick dielectric reducing the capacitance of the overlap on the source.
Although these two approaches are useful, they are not without their shortcomings. One shortcoming with these two approaches is that the thickness of the silicon pillar depends on the resolution of the photolithographic method used either to etch the pillar directly or to open the window in the dielectric layer. Thus at present there is no hope of producing very thin pillars (i.e. thinner than 50 nm) with conventional photolithography, which consequently limits the effectiveness of the gate coupling phenomenon.
Another shortcoming with these two approaches is that in a vertical transistor, the depth of the junctions is equal to the thickness of the silicon pillar. For a relatively thick pillar, the junction depth can therefore be very large compared to the length of the channel, which is extremely unfavorable in terms of controlling the effects of short channels.
Accordingly, a need exist to overcome these shortcomings.